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Ordering number : EN* 5192B
CMOS LSI
LC895195
ATA-PI (IDE) CD-ROM Decoder LSI
Preliminary Overview
The LC895195 is a CD-ROM decoder LSI that includes both an on-chip IDE interface that was developed jointly with Western Digital and an on-chip subcode ECC function.
Package Dimensions
unit: mm 3214-SQFP144
[LC895195]
Features
* ATA-PI (IDE) interface * Supports 16x playback (with IORDY) - Using x16 70 ns DRAMs * 16.6 MB/s transfer rate: Using x16 70 ns DRAMs * 8.33 MB/s transfer rate: Using x8 70 ns DRAMs * Supports the use of from 1 M to 32 M of buffer RAM. (DRAM) * Allows the user to arbitrarily set the CD main channel, C2 flag and subcode areas in buffer RAM. * Batch transfer function (function for transferring the CD main channel, C2 flag and subcode data in one operation) * Multi-transfer function (function for sending multiple blocks in one operation)
SANYO: SQFP144
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Maximum supply voltage I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering heat resistances (pins only) I/O current Note: * Per cell for basic I/O cells II, IO max Symbol VDD max VI, VO max Pd max Topr Tstg 10 seconds Ta = 25C Ta = 25C Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 550 -30 to +75 -55 to +125 235 20* Unit V V mW C C C mA
Allowable Operating Ranges at Ta = -30 to +75C, VSS = 0 V
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions min 4.5 0 typ 5.0 max 5.5 VDD Unit V V
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N3097HA (OT)/22896HA (OT) No. 5192-1/8
LC895195 DC Characteristics at VSS = 0 V, VDD = 4.5 to 5.5 V, Ta = -30 to +75C
Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output high level voltage Output high level voltage Input leakage current Output leakage current Pull-up resistance Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOL5 VOL4 IIL IOZ RUP Applicable Pins* (See below) TTL compatible: (1) min 2.2 0.8 2.2 0.8 2.2 0.8 VDD - 2.1 0.4 VDD - 2.1 0.4 VDD - 2.1 0.4 0.4 0.4 -10 -10 40 80 +10 +10 160 typ max Unit V V V V V V V V V V V V V V A A k
TTL compatible, with pull-up resistor: (9)
TTL compatible, Schmitt: (2), and (10) IOH = -2 mA IOL = 2 mA IOH = -8 mA IOL = 8 mA IOH = -4 mA IOL = 24 mA IOL = 24 mA: (8) IOL = 2 mA: (4) VI = VSS, VDD: (1), (2),and (10) For high-impedance outputs: (6), and (10) (9)
(5), (7), and (9)
(3)
(6), and (10)
Note: * The entries in the "Applicable Pins" column specify the following pin sets. [Input] 1: CSCTRL, SUA0 to SUA6, TEST0 to TEST4 2: SBSO, SCOR, WFCK, ZCS, ZDIOR, ZDIOW, ZDMACK, ZHRST, ZRESET, ZRD, ZWR, BCK, C2PO, LRCK, SDATA, DA0 to DA2, ZCS1FX, ZCS3FX [Output] 3: MCK, MCK2 4: ZRSTCPU, ZRSTIC, ZINT1 5: ZINT, ZSWAIT 6: DMARQ, HINTRQ 7: RA0 to RA9, ZCAS0, ZCAS1, ZLWE, ZOE, ZRAS0, ZRAS1, ZUWE, EXCK 8: IORDY, ZIOCS16 [I/O] 9: D0 to D7, IO0 to IO15 10: DD0 to DD15, ZDASP, ZPDIAG Note: XTAL, XTALCK The above pins are not included in the DC characteristics.
Sample Recommended Oscillator Circuit
R1 = 120 k R2 = 47 k C1 = 30 pF For a crystal oscillator frequency of 16.9344 MHz. Alternatively: R1 = 3.3 k R2 = None C1 = 5 pF For a crystal oscillator frequency of 33.8688 MHz. For an oscillator frequency of 33.8688, the third harmonic is used. This means that precise component values will be influenced by the printed circuit board. Consult the manufacturer of the crystal to determine the circuit constants for this frequency.
No. 5192-2/8
LC895195 Pin Functions
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IO0 IO1 IO2 IO3 IO4 IO5 VSS0 VDD IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 EXCK WFCK SBSO TEST1 TEST2 TEST3 Symbol VSS0 ZRAS0 ZRAS1 VSS0 ZCAS0 ZCAS1 VSS0 ZOE ZUWE ZLWE RA0 RA1 RA2 RA3 RA4 RA5 RA6 VDD VSS0 RA7 RA8 RA9 VSS0 TEST0 Type P O O P O O P O O O O O O O O O O P P O O O P NC NC NC NC NC NC B B B B B B P P B B B B B B B B B B O I I SUB-CODE I/O Data buffer DRAM data I/O These pins have built-in pull-up resistors. Data buffer DRAM data I/O These pins have built-in pull-up resistors. RA7 to RA9 are the data buffer DRAM address signal output. RA0 to RA6 are the data buffer DRAM address signal output. Buffer RAM output enable Buffer RAM upper write enable Buffer RAM lower write enable Buffer DRAM CAS signal output 0 (This pin is used normally.) Buffer DRAM CAS signal output 1 Buffer DRAM RAS signal output 0 (This pin is used normally.) Buffer DRAM RAS signal output 1 Function
Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground.
No. 5192-3/8
LC895195
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VSS0 SDATA BCK LRCK C2PO MCK2 VSS0 XTALCK XTAL VSS0 VDD MCK VSS0 ZRSTIC CSCTRL ZRESET ZRD ZWR ZCS VSS0 SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VDD VSS0 D0 D1 D2 D3 D4 D5 D6 D7 ZINT Symbol SCOR VSS0 VSS0 TEST4 VSS0 VSS0 ZINT1 VSS0 VSS0 VSS0 Type I P P I P P O P P P NC NC P I I I I O P I O P P O P I I I I I I P I I I I I I I P P B B B B B B B B O Interrupt request signal output to the microcontroller Microcontroller data signals These pins have built-in pull-up resistors. Microcontroller register select signals Reset signal to drive reset IC Selects active high or active low for the microcontroller CS line. LSI reset Microcontroller data read signal input Microcontroller data write signal input Input for the register chip select signal from the microcontroller XTALCK 1/1, 1/2, and stop output Xtal oscillator input Xtal oscillator output XTALCK 1/1, 1/2, 1/512, and stop output CD-DSP interface Interrupt request signal output to the microcontroller from the IDE block. Test input. This must be tied low. SUB-CODE input pin Function
Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground.
Continued on next page. No. 5192-4/8
LC895195
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Symbol ZRSTCPU ZWAIT ZHRST ZDASP ZCS3FX ZCS1FX DA2 VSS0 VDD DA0 ZPDIAG DA1 ZIOCS16 HINTRQ ZDMACK VSS1 IORDY ZDIOR ZDIOW DMARQ DD15 VSS1 DD0 DD14 DD1 DD13 VSS1 VDD DD2 DD12 DD3 VSS1 DD11 DD4 DD10 VSS1 VDD DD5 DD9 DD6 VSS1 DD8 DD7 VDD Type O O I B I I I P P I B I O O I P O I I O B P B B B B P P B B B P B B B P P B B B P B B P ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus ATAPI control signals ATAPI control signals ATAPI control signals Function
Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground.
No. 5192-5/8
LC895195 Pin Functions 1. ATA-PI Pins * ZCS1FX (input) Chip select signal for selecting the command block register. * ZCS3FX (input) Chip select signal for selecting the control block register. * DA0 to DA2 (input) Address for accessing the ATAPI registers. * ZDASP (I/O) Drive 1 is output and drive 0 is input. Signal used to indicate to drive 0 that drive 1 exists. An external pull-up resistor must be connected to this pin. * DD0 to DD15 (I/O) 16-bit data bus. Can be used for either 8-bit or 16-bit data transfers. * ZDIOR (input) Read strobe signal from the host. * ZDIOW (input) Write strobe signal from the host. * ZDMACK (input) Acknowledge signal from the host in response to the drive DMARQ request signal during DMA transfers. The pin circuit does not include a pull-up resistor. * DMARQ (output) Drive request signal during DMA transfers * HINTRQ (output) Drive interrupt signal to the host * ZIOCS16 (output) Signal asserted by the drive when the drive supports 16-bit transfers. This signal is not asserted during DMA transfers. * IORDY (output) Signal that indicates that the drive has completed response preparations during data transfers. This signal is low when the drive is not ready. * ZPDIAG (I/O) Signal asserted by drive 1 to inform drive 0 that diagnostics have completed. An external pull-up resistor must be connected to this pin. * ZHRST (input) Reset signal from the host. The pin circuit does not include a pull-up resistor. 2. MC (microcontroller) Interface Pins * ZCS (input) Microcontroller chip select signal * CSCTRL (input) Microcontroller chip select logic selection signal High - ZCS functions as an active low signal. Low - ZCS functions as an active high signal. * ZRD, ZWR, SUA0 to SUA6 (input) Microcontroller interface control signals. The SUA0 to SUA6 pins are address lines.
No. 5192-6/8
LC895195 * ZSWAIT (output) When the microcontroller is accessing RAM, the sub-CPU must wait if this pin is low. * D7 to D0 (I/O) Microcontroller data bus. Pull-up resistors are built in. * ZINT (output) Interrupt request signal output to the microcontroller. A pull-up resistor is built in. * ZINT1 (output) Interrupt request signal output from the IDE block to the microcontroller. An external pull-up resistor must be connected to this pin. 3. Buffer RAM Pins * IO0 to IO15 (I/O) Buffer DRAM data bus. A pull-up resistor is built in. * RA0 to RA9 (output) Buffer RAM address lines. * ZRAS0, ZRAS1 (output) Buffer DRAM RAS outputs. Normally, ZRAS0 is used, but if two 1-Mb (64k x 16 bits) chips are used, then both ZRAS0 and ZRAS1 are used, one for each of the chips. * ZCAS0, ZCAS1 (output) Buffer DRAM CAS outputs. Normally, ZCAS0 is used, but if two 1-Mb (64k x 16 bits) chips are used, then both ZCAS0 and ZCAS1 are used, one for each of the chips. When using a two-CAS type DRAM, connect ZCAS0 to UCAS, and ZCAS1 to LCAS. * ZOE (output) Buffer DRAM read output signal. * ZUWE, ZLWE (output) Buffer DRAM write output signals. Connected the corresponding DRAM pins. 4. Subcode Interface Pins * EXCK, WFCK, SBSO, SCOR (input or output) These are the subcode interface connections. The LC895195 acquires subcode data by connection with the CDDSP and sends that data to the host. 5. CD-DSP Data Pins * BCK, SDATA, LRCK, C2PO (input) The LC895195 reads in the CD-ROM data by connecting to the CD-DSP. The C2PO pin is used for the C2 flags. 6. Other Pins * ZRESET (input) This is the LC895195 reset pin. The LC895195 is reset by a low level on this pin. This pin must be held low for at least 1 s when power is first applied. * XTALCK, XTAL These pins can drive a 16.9344-MHz or 33.8688-MHz oscillator. Alternatively, an external clock can be input to the XTALCK pin. * MCK (output) This pin outputs either the XTALCK frequency or that frequency divided by 2. This output can be turned off. * MCK2 (output) This pin outputs either the XTALCK frequency or that frequency divided by 512. This output can be turned off. * ZRSTIC (output) This pin can be set to output a low level either by writing to the microcontroller write register R46 bit 7 (ZSYSRTS) or by setting the ZHRST pin (pin 103) low. This pin goes to the high-impedance state when both ZSYSRST and ZHRST are high. Since this pin has an open-drain circuit, an external pull-up resistor must be used.
No. 5192-7/8
LC895195 * ZRSTCPU (output) When an ATAPI soft reset command (08h) has been received, this pin generates a low-going pulse with a duration of about 1 ms (when the XTALCK frequency is 34 MHz). (This pulse will have a duration of about 2 ms when the XTALCK frequency is 16 MHz.) At this time a microcontroller interrupt will be generated. When the ZRESET pin (pin 78) becomes active (low), the ZRESET signal will be output without change to the ZRSTCPU pin. Since this pin has an open-drain circuit, an external pull-up resistor must be used.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5192-8/8

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